T4240QDS-PB Development Kit For 24 Virtual Core QorIQ T4240 Processor - Boxed Product (Development Kits) (Alt: T4240QDS-PB) RoHS : Not Compliant
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The LS2085A Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS2085A Layerscape Architecture processor. The LS2085AQDS provides validation and SW development platform for the Freescale LS2085A processor series, with a complete debugging environment.
LS2085A SoC Overview ------------------ The LS2085A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications.
The LS2085A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by the AIOP - Data path acceleration architecture (DPAA2) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution (WRIOP) - Queue and Hardware buffer management for scheduling, packet sequencing, and congestion management, buffer allocation and de-allocation (QBMan) - Cryptography acceleration (SEC) at up to 10 Gbps - RegEx pattern matching acceleration (PME) at up to 10 Gbps - Decompression/compression acceleration (DCE) at up to 20 Gbps - Accelerated I/O processing (AIOP) at up to 20 Gbps - QDMA engine - 16 SerDes lanes at up to 10.3125 GHz - Ethernet interfaces - Up to eight 10 Gbps Ethernet MACs - Up to eight 1 / 2.5 Gbps Ethernet MACs - High-speed peripheral interfaces - Four PCIe 3.0 controllers, one supporting SR-IOV - Additional peripheral interfaces - Two serial ATA (SATA 3.0) controllers - Two high-speed USB 3.0 controllers with integrated PHY - Enhanced secure digital host controller (eSDXC/eMMC) - Serial peripheral interface (SPI) controller - Quad Serial Peripheral Interface (QSPI) Controller - Four I2C controllers - Two DUARTs - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - Support for hardware virtualization and partitioning enforcement - QorIQ platform's trust architecture 3.0 - Service processor (SP) provides pre-boot initialization and secure-boot capabilities
LS2085AQDS board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - XAUI - XFI - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects and two DIMM connectors. Support is up to 1600MT/s. -IFC/Local Bus - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - One in-socket 128 MB NOR flash 16-bit data bus - One 512 MB NAND flash with ECC support - IFC Test Port - PromJet Port - FPGA connection - USB 3.0 - Two high speed USB 3.0 ports - First USB 3.0 port configured as Host with Type-A connector - Second USB 3.0 port configured as OTG with micro-AB connector - SDHC: PCIe x1 Right Angle connector for supporting following cards - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only - 4-bit eMMC Card Rev 4.4 (1.8V only) - 8-bit eMMC Card Rev 4.5 (1.8V only) - SD Card Rev 2.0 and Rev 3.0 - DSPI: 3 high-speed flash Memory for storage - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 8 MB high-speed flash Memory (up to 104 MHz) - 512 MB low-speed flash Memory (up to 40 MHz) - QSPI: via NAND/QSPI Card - 4 I2C controllers - Two SATA onboard connectors - UART - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support