T4240QDS-PB Development Kit For 24 Virtual Core QorIQ T4240 Processor


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T4240QDS-PB Development Kit For 24 Virtual Core QorIQ T4240 Processor - Boxed Product (Development Kits) (Alt: T4240QDS-PB) RoHS : Not Compliant

Original new and unused with factory package, Stock on hand, ship out immediately

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      The T4240QDS is a flexible development system that supports the 24 virtual core QorIQ T4240 processor. With its 1.8 GHz suite of cores and rich input/output (I/O) mix, the board is intended for development of T4240 in enterprise and datacenter networking, telecom and industrial applications, where the high-performance, high-efficiency e6500 cores and integration make it very well suited as a combined control and data plane processor. The T4240QDS can help shorten time to market. The board is built to allow the exercising of most capabilities of the device and can serve as a reference for system-level hardware development by providing a comparison tool for customer-specific board implementations. It can also be used for customer software development and performance evaluation.

      Key Features

      Core Complex

      • 12 dual-threaded e6500 cores built on Power Architecture® technology
      • Up to 1.8 GHz each, 6.0 DMIPS/MHz per core
      • Each four-core cluster shares a 2 MB L2 cache
      • Three levels of instructions: user, supervisor, hypervisor
      • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
      • Advanced power management saving modes include state retention during power gating

      Basic Peripherals and Interconnect

      • CoreNet platform L3 cache
      • Hierarchical interconnect fabric
        • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
      • Additional peripheral interfaces:
        • Two high-speed USB 2.0 controllers with integrated PHYs
        • Enhanced secure digital host controller (SD/MMC/eMMC)
        • Enhanced serial peripheral interface (eSPI)
        • Four I²C controllers
        • Two DUARTS
        • Integrated flash controller supporting NAND and NOR flash memory

      Accelerators and Memory Controller

      • Three 64-bit DDR3/3L SDRAM memory controller with ECC support
      • Up to 2.13 GT/s
      • Memory pre-fetch engine
      • Datapath Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
        • Packet parsing, classification, and distribution at up to 50 Gbps
        • Queue management for scheduling, packet sequencing, and congestion management
        • Hardware buffer management for buffer allocation and de-allocation
        • Cryptography acceleration (SEC 5.0) at up to 40 Gbps
        • RegEx pattern matching acceleration at up to 10 Gbps
        • Decompression/compression acceleration at up to 20 Gbps
        • DPAA chip-to-chip interconnect via RapidIO® Message Manager
        • Security with trust architecture

      Networking Elements

      • 32 SerDes lanes at up to 10.3125 GHz
      • Ethernet Interfaces
        • Up to four 10 Gbps Ethernet MACs
        • Up to 16 1 Gbps Ethernet MACs
      • High-speed peripheral interfaces
        • Four PCI Express® 1.1/2.0/3.0 controllers
        • Endpoint SR-IOV
        • Two serial RapidIO® 2.0 controllers/ports running at up to 5 GHz
        • Interlaken Look-Aside interface for serial TCAM connection
      • DMA
        • Dual eight channel

      Additional Features

      • Support for hardware virtualization and partitioning enforcement
        • Extra privileged level for hypervisor support
        • Logical to real address translation
        • Virtual core aware MMU/TLB
        • vMPIC (virtualized interrupt controller)/virtual core capable PPC cores
        • vDMA (user level DMA engine)
        • PAMUv2 (I/O MMU supporting paging)
        • DPAA (Ethernet MAC virtualization, accelerator virtualization)
        • Trust architecture secure boot
        • Secure boot, secure debug, tamper detection, volatile key storage, alternate image and key revocation